The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 30, 2014

Filed:

Apr. 27, 2010
Applicant:

Gunnar Forsberg, Stockholm, SE;

Inventor:

Gunnar Forsberg, Stockholm, SE;

Assignee:

Transmode Systems AB, Stockholm, SE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04J 3/06 (2006.01); H04J 4/00 (2006.01); H04W 4/00 (2009.01); H04J 3/16 (2006.01); H04L 5/26 (2006.01); H04L 7/00 (2006.01); H04L 5/14 (2006.01); H04L 1/00 (2006.01);
U.S. Cl.
CPC ...
H04J 3/1664 (2013.01); H04L 5/26 (2013.01); H04L 7/0083 (2013.01); H04L 5/14 (2013.01); H04L 1/0025 (2013.01);
Abstract

In a data transmission system, a first node receives at least two sets of input data signals including at least two signals being based on different synchronization sources. The first node extracts a respective clock signal representing the embedded clock signals from the sources, samples and formats these signals for transmission according to a TDM structure. The TDM formatted signals are transmitted as at least one bit stream over a transmission medium to at least one second node, where the bit stream is demultiplexed into at least two sets of output data signals respective demultiplexed clock signals representing the sampled clock signals. A jitter attenuating mechanism reduces an amount of frequency jitter to below a predefined level to produce a respective clock signal having a synchronization quality superior to that of the demultiplexed clock signals. An interface module recombines each data signal with its associated clock signal.


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