The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 30, 2014

Filed:

Mar. 15, 2013
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventor:

Seul-Ki Oh, Gyeonggi-do, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 16/14 (2006.01); H01L 27/115 (2006.01); H01L 29/66 (2006.01); H01L 29/792 (2006.01);
U.S. Cl.
CPC ...
G11C 16/14 (2013.01); H01L 27/11551 (2013.01); H01L 27/11578 (2013.01); H01L 29/66477 (2013.01); H01L 29/7926 (2013.01);
Abstract

Disclosed are a non-volatile memory device and a method of fabricating the same. The non-volatile memory device includes a semiconductor substrate including a plurality of active regions and a pair of first pillars protruding from each active region. A pair of drain selection lines surround each pillar of the pair of first pillars. A pair of second pillars, wherein each second pillar is disposed over a corresponding first pillar, of the pair of the first pillars, and is formed of a semiconductor material. A plurality of word lines and a source selection line form a stack that surrounds the pair of second pillars. A source line is formed over and connected with the pair of second pillars. Drain contacts are formed at both sides of each active region except between pairs of the drain selection lines. A bit line is formed over and connected with the drain contacts.


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