The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 30, 2014
Filed:
Dec. 05, 2012
Applicant:
SK Hynix Inc., Icheon-si Gyeonggi-do, KR;
Inventors:
Noh Yong Park, Seoul, KR;
Hyung Seok Kim, Seoul, KR;
Assignee:
SK Hynix Inc., Gyeonggi-do, KR;
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/14 (2006.01); G11C 16/04 (2006.01); G11C 16/16 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G11C 16/04 (2013.01); G11C 16/16 (2013.01); G11C 16/3445 (2013.01); G11C 16/0483 (2013.01);
Abstract
A semiconductor memory device includes a memory array including a plurality of memory cells, and a peripheral circuit configured to perform an erase operation by supplying a first erase voltage to selected memory cells and perform an erase verify operation by supplying an erase verify voltage to the selected memory cells, wherein the peripheral circuit is configured to increase the first erase voltage to a first level at a first rising rate for a first rising period and increase the first erase voltage to a first target level at a second rising rate lower than the first rising rate for a second rising period.