The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 30, 2014
Filed:
Jul. 30, 2012
Rouying Zhan, Gilbert, AZ (US);
Amaury Gendron, Scottsdale, AZ (US);
Chai Ean Gill, Chandler, AZ (US);
Rouying Zhan, Gilbert, AZ (US);
Amaury Gendron, Scottsdale, AZ (US);
Chai Ean Gill, Chandler, AZ (US);
Freescale Semiconductor Inc., Austin, TX (US);
Abstract
Methods are provided for producing stacked electrostatic discharge (ESD) clamps. In one embodiment, the method includes providing a semiconductor substrate in which first and second serially-coupled transistors are formed. The first transistor includes a first well region having a first lateral edge partially forming the first transistor's base. The second transistor including a second well region having a second lateral edge partially forming the second transistor's base. Third and fourth well regions are formed in the first and second transistors, respectively, and extend a different distance into the substrate than do the well regions of the first and second transistors. The third well region has a third lateral edge separated from the first lateral edge by a first spacing dimension D. The fourth well region has a fourth lateral edge separated from the second lateral edge by a second spacing dimension D, which is different than D