The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 30, 2014
Filed:
May. 02, 2011
Applicant:
Shinichiro Matsunaga, Matsumoto, JP;
Inventor:
Shinichiro Matsunaga, Matsumoto, JP;
Assignee:
Fuji Electric Co., Ltd., Kawasaki-Shi, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 21/265 (2006.01); H01L 29/45 (2006.01);
U.S. Cl.
CPC ...
H01L 29/41766 (2013.01); H01L 29/4236 (2013.01); H01L 29/66659 (2013.01); H01L 29/7835 (2013.01); H01L 21/26586 (2013.01); H01L 29/456 (2013.01); H01L 29/66787 (2013.01);
Abstract
A semiconductor device having a low on resistance and high integration level with respect to the surface area of a substrate is provided. In the semiconductor device, a first trench, a second trench, and a third trench are provided in an element formation region provided on a semiconductor substrate. Metal is deposited within the first trench and second trench, to form a drain electrode and a source electrode, respectively. Polysilicon is deposited inside the third trench with a gate insulating film intervening, and a gate electrode is formed.