The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 30, 2014

Filed:

Jun. 05, 2013
Applicant:

Panasonic Corporation, Osaka, JP;

Inventors:

Yuko Okumoto, Osaka, JP;

Akihito Miyamoto, Osaka, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/00 (2006.01); H01L 51/00 (2006.01); H01L 21/00 (2006.01); H01L 21/332 (2006.01); H01L 51/40 (2006.01); H01L 51/05 (2006.01); H01L 29/786 (2006.01); H01L 27/32 (2006.01);
U.S. Cl.
CPC ...
H01L 51/0529 (2013.01); H01L 29/786 (2013.01); H01L 51/004 (2013.01); H01L 27/3274 (2013.01); H01L 27/3262 (2013.01); H01L 51/0533 (2013.01); H01L 51/0541 (2013.01); H01L 51/0545 (2013.01); H01L 2251/5315 (2013.01); H01L 51/0037 (2013.01);
Abstract

A thin-film transistor including: a gate electrode that is located above a substrate; a gate insulating layer that faces the gate electrode; a partition that defines an opening and has higher liquid repellency than liquid repellency of the gate insulating layer, the opening having a surface of the gate insulating layer therewithin; a semiconductor layer that faces the gate electrode with the gate insulating layer interposed therebetween and is formed within the opening by an application method; a source electrode and a drain electrode that are electrically connected to the semiconductor layer; and an intermediate layer that is made of the same material as a material of the partition and is located between the gate insulating layer and the semiconductor layer, wherein the intermediate layer is discretely present above the gate insulating layer.


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