The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 30, 2014

Filed:

Sep. 05, 2012
Applicants:

Sung-wook Jung, Gyeonggi-do, KR;

Yun-kyoung Lee, Gyeonggi-do, KR;

Young-soo Ahn, Gyeonggi-do, KR;

Tae-hwa Lee, Gyeonggi-do, KR;

Inventors:

Sung-Wook Jung, Gyeonggi-do, KR;

Yun-Kyoung Lee, Gyeonggi-do, KR;

Young-Soo Ahn, Gyeonggi-do, KR;

Tae-Hwa Lee, Gyeonggi-do, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for fabricating a nonvolatile memory device includes forming a stacked structure having a plurality of interlayer dielectric layers and a plurality of sacrificial layers wherein interlayer dielectric layers and sacrificial layers are alternately stacked over a substrate, forming a first hole exposing a part of the substrate by selectively etching the stacked structure, forming a first insulation layer in the first hole, forming a second hole exposing the part of the substrate by selectively etching the first insulation layer, and forming a channel layer in the second hole.


Find Patent Forward Citations

Quick Actions:

Jung, Sung-Wook. (2014). Method for fabricating 3d nonvolatile memory device with vertical channel hole (U.S. Patent No. 8921182). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8921182

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