The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 30, 2014

Filed:

Feb. 29, 2012
Applicants:

Jun Liu, Milpitas, CA (US);

Albert Ratnakumar, San Jose, CA (US);

Mark T. Chan, San Jose, CA (US);

Irfan Rahim, Milpitas, CA (US);

Inventors:

Jun Liu, Milpitas, CA (US);

Albert Ratnakumar, San Jose, CA (US);

Mark T. Chan, San Jose, CA (US);

Irfan Rahim, Milpitas, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/338 (2006.01);
U.S. Cl.
CPC ...
Abstract

Asymmetric transistors such as asymmetric pass transistors may be formed on an integrated circuit. The asymmetric transistors may have gate structures. Symmetric pocket implants may be formed in source-drains on opposing sides of each transistor gate structure. Selective heating may be used to asymmetrically diffuse the implants. Selective heating may be implemented by patterning the gate structures on a semiconductor substrate so that the spacing between adjacent gate structures varies. A given gate structure may be located between first and second adjacent gate structures spaced at different respective distances from the given gate structure. A larger gate structure spacing leads to a greater substrate temperature rise than a smaller gate structure spacing. The pocket implant diffuses more in portions of the substrate with the greater temperature rise, producing asymmetric transistors. Asymmetric pass transistors may be controlled by static control signals from memory elements to implement circuits such as programmable multiplexers.


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