Memory controller, memory system, semiconductor integrated circuit, and memory control method

Abstract

A memory controller () according to this invention includes: a command generation unit () which generates access commands each including a physical address, based on an access request including a logical address indicating a rectangular area in image data; and a command issuance unit () which issues, to a memory (0), the access commands generated by the command generation unit (). The command generation unit () includes a group determination unit () which determines a group to which a bank including data to be accessed belongs, based on the physical address corresponding to the access request. The command generation unit () generates a pair of a first and a second access commands which share a prefetch buffer between two banks belonging to different groups, when data to be accessed is continuous across two banks belonging to different groups.