The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 23, 2014

Filed:

Nov. 25, 2013
Applicant:

The Regents of the University of California, Oakland, CA (US);

Inventors:

Kang-Lung Wang, Santa Monica, CA (US);

Chih-Kong K. Yang, Pacific Palisades, CA (US);

Dejan Markovic, Los Angeles, CA (US);

Fengbo Ren, Los Angeles, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/06 (2006.01); G11C 13/00 (2006.01); G11C 11/16 (2006.01);
U.S. Cl.
CPC ...
G11C 11/1673 (2013.01); G11C 7/062 (2013.01); G11C 13/0004 (2013.01); G11C 11/16 (2013.01); G11C 13/0007 (2013.01); G11C 2207/063 (2013.01); G11C 2013/0054 (2013.01); G11C 13/004 (2013.01);
Abstract

As memory geometries continue to scale down, current density of magnetic tunnel junctions (MTJs) make conventional low current reading scheme problematic with regard to performance and reliability. A body-voltage sense circuit (BVSC) short pulse reading (SPR) circuit is described using body connected load transistors and a novel sensing circuit with second stage amplifier which allows for very short read pulses providing much higher read margins, less sensing time, and shorter sensing current pulses. Simulation results (using 65-nm CMOS model SPICE simulations) show that our technique can achieve 550 mV of read margin at 1 ns performance under a 1 V supply voltage, which is greater than reference designs achieve at 5 ns performance.


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