Nor flash memory array structure, mixed nonvolatile flash memory and memory system comprising the same

Abstract

A NOR flash memory array structure is provided, comprising: a substrate (); and a two dimensional memory array structure formed on the substrate () and comprising: a plurality of memory cell columns arranged in a first direction, and each memory cell column including a plurality of memory cells (), in which each memory cell () comprises: a channel region () located on the substrate (), a gate structure located on the channel region () and formed by a tunneling oxide layer (), a silicon nitride layer (), a barrier oxide layer () and a polysilicon gate layer () stacked sequentially, a source region () and a drain region () located at a first edge and a second edge of the gate structure respectively; a plurality of word lines WL; a source line SL for connecting the source regions of all the memory cells; and a plurality of bit lines BL.