The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 16, 2014
Filed:
Aug. 17, 2009
Lyndon G. Pierson, Albuquerque, NM (US);
Edward L. Witzke, Edgewood, NM (US);
Thomas D. Tarman, Edgewood, NM (US);
Perry J. Robertson, Albuquerque, NM (US);
John M. Eldridge, Bosque Farms, NM (US);
Philip L. Campbell, Albuquerque, NM (US);
Lyndon G. Pierson, Albuquerque, NM (US);
Edward L. Witzke, Edgewood, NM (US);
Thomas D. Tarman, Edgewood, NM (US);
Perry J. Robertson, Albuquerque, NM (US);
John M. Eldridge, Bosque Farms, NM (US);
Philip L. Campbell, Albuquerque, NM (US);
Sandia Corporation, Albuquerque, NM (US);
Abstract
A faithful execution system includes system memory, a target processor, and protection engine. The system memory stores a ciphertext including value fields and integrity fields. The value fields each include an encrypted executable instruction and the integrity fields each include an encrypted integrity value for determining whether a corresponding one of the value fields has been modified. The target processor executes plaintext instructions decoded from the ciphertext while the protection engine is coupled between the system memory and the target processor. The protection engine includes logic to retrieve the ciphertext from the system memory, decrypt the value fields into the plaintext instructions, perform an integrity check based on the integrity fields to determine whether any of the corresponding value fields have been modified, and provide the plaintext instructions to the target processor for execution.