The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 16, 2014

Filed:

Jun. 12, 2008
Applicants:

Tommi Kanerva, Tampere, FI;

Pasi Kolinummi, Kangasala, FI;

Mika Koikkalainen, Tampere, FI;

Inventors:

Tommi Kanerva, Tampere, FI;

Pasi Kolinummi, Kangasala, FI;

Mika Koikkalainen, Tampere, FI;

Assignee:

Nokia Corporation, Espoo, FI;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04B 1/56 (2006.01); H04L 5/14 (2006.01); H04L 12/24 (2006.01);
U.S. Cl.
CPC ...
H04L 41/083 (2013.01); H04L 41/145 (2013.01); H04L 5/14 (2013.01);
Abstract

Suitably arranged circuits located on a die surface of respective multiple dies are operatively connected via a physical link, which is configured for full-duplex operation. Data information content is transferred between the operatively connected suitably arranged circuits via the full-duplex physical link which is configured as a fragmented data interconnected (FDI) physical link allowing peer-to-peer operation and pipelining. The data information content is carried in data fragments by a self-contained data packet structure. In one embodiment a device comprises a first suitably arranged and configured circuit located on a die surface, a second suitably arranged and configured circuit located on a die surface and a full-duplex physical link arranged and configured for operatively connecting the first circuit located on the die surface to the second circuit located on the die surface for transferring data information content between the first circuit and the second circuit.


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