The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 16, 2014
Filed:
Sep. 03, 2013
Shinji Watanabe, Tokyo, JP;
Nobuhiro Mikami, Tokyo, JP;
Junya Sato, Tokyo, JP;
Kenichiro Fujii, Tokyo, JP;
Katsumi Abe, Tokyo, JP;
Atsumasa Sawada, Tokyo, JP;
Shinji Watanabe, Tokyo, JP;
Nobuhiro Mikami, Tokyo, JP;
Junya Sato, Tokyo, JP;
Kenichiro Fujii, Tokyo, JP;
Katsumi Abe, Tokyo, JP;
Atsumasa Sawada, Tokyo, JP;
NEC Corporation, Tokyo, JP;
Abstract
An object of the present invention is to allow stress that may be applied to a semiconductor package to be suppressed, when the semiconductor package is mounted on a curved board. In a mount board, a semiconductor packageis mounted on a curved boardincluding a curved surface on at least a portion thereof. The curved boardincludes a pedestal portiondisposed on a region of the curved surface portion where the semiconductor packageis mounted and having an upper surface thereof formed flat, and a plurality of pad portionsdisposed on the flat surface of the pedestal portion. The pedestal portionis formed of an insulating material. The semiconductor packageis mounted on the pad portions