The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 16, 2014

Filed:

Aug. 29, 2011
Applicants:

Ki Joong Kim, Jeollabuk-do, KR;

Youn Suk Kim, Gyunggi-do, KR;

Jun Goo Won, Gyunggi-do, KR;

Jae Hyouck Choi, Gyunggi-do, KR;

Sang Wook Park, Gyunggi-do, KR;

Chul Hwan Yoon, Gyunggi-do, KR;

Inventors:

Ki Joong Kim, Jeollabuk-do, KR;

Youn Suk Kim, Gyunggi-do, KR;

Jun Goo Won, Gyunggi-do, KR;

Jae Hyouck Choi, Gyunggi-do, KR;

Sang Wook Park, Gyunggi-do, KR;

Chul Hwan Yoon, Gyunggi-do, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03H 7/38 (2006.01); H03H 7/42 (2006.01); H03F 3/60 (2006.01); H03H 7/48 (2006.01); H03F 3/21 (2006.01); H01L 25/16 (2006.01); H01L 23/66 (2006.01); H05K 1/16 (2006.01);
U.S. Cl.
CPC ...
H03H 7/42 (2013.01); H01L 25/16 (2013.01); H03F 2200/537 (2013.01); H03F 3/602 (2013.01); H03H 7/48 (2013.01); H03F 2200/541 (2013.01); H01L 23/66 (2013.01); H03F 3/211 (2013.01); H05K 1/165 (2013.01);
Abstract

There are provided a power combiner implemented by a printed circuit board, a power amplifying module having the same, and a signal transceiving module. The power combiner includes: a primary wiring unit formed on one surface of a printed circuit board, receiving a plurality of balance signals having positive balance signals and negative balance signals, and including a plurality of positive primary wirings and a plurality of negative primary wirings, wherein the plurality of positive primary wirings are spaced apart from each other by a predetermined interval, the plurality of negative primary wirings are spaced apart from each other by a predetermined interval, one ends of the plurality of positive primary wirings are connected in common to thereby receive the plurality of positive balance signals, one ends of the plurality of negative primary wirings are connected in common to thereby receive the plurality of negative balance signals, and the other ends of the plurality of positive primary wirings and the other ends of the plurality of negative primary wirings are connected to each other to thereby form a loop; and a secondary wiring unit formed on the other surface of the printed circuit board, and including a secondary wiring combining powers of the plurality of balance signals from the primary wirings forming the loop to thereby output a single end signal.


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