The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 16, 2014

Filed:

Jul. 29, 2013
Applicant:

Futurewei Technologies, Inc., Plano, TX (US);

Inventors:

Lawrence E. Connell, Naperville, IL (US);

Daniel P. McCarthy, Elk Grove Village, IL (US);

Brian T. Creed, Batavia, IL (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03H 11/16 (2006.01); H03H 11/22 (2006.01);
U.S. Cl.
CPC ...
H03H 11/22 (2013.01);
Abstract

An apparatus comprising a frequency divider comprising a first latch configured to receive a first clock signal and a complement of the first clock signal and to generate a first latch first output, and a second latch coupled to the first latch in a toggle-flop configuration, a first output circuit comprising a p-channel transistor, wherein the gate of a p-channel transistor is configured to receive the first clock signal, and a n-channel transistor, wherein the drain of the p-channel transistor is directly connected to the drain of a n-channel transistor, wherein the gate of the n-channel transistor is configured to receive the first latch first output, wherein the source of the n-channel transistor is configured to receive the complement of the first clock signal, and wherein the first output circuit is configured to generate an in-phase reference signal, and a second output circuit configured to generate a quadrature signal.


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