The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 16, 2014
Filed:
Aug. 12, 2013
Applicant:
Xilinx, Inc., San Jose, CA (US);
Inventors:
James E. Ogden, Tracy, CA (US);
James M. Simkins, Park City, UT (US);
Uma Durairajan, Sunnyvale, CA (US);
Subodh Kumar, San Jose, CA (US);
Assignee:
Xilinx, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/00 (2006.01); H03L 7/10 (2006.01); H03K 17/22 (2006.01); H02M 1/00 (2006.01);
U.S. Cl.
CPC ...
H03L 7/105 (2013.01); H03K 17/223 (2013.01); H02M 2001/0032 (2013.01);
Abstract
An integrated circuit and method for using a synchronous reset pulse to reset a circuitry comprising a plurality of clock domains are disclosed. For example, the method of the present disclosure provides a reset signal that is synched to one clock, takes the synchronous signal and resets circuits in a plurality of clock domains. In order to reset a portion of the circuit which is in a particular clock domain, the reset needs to be synchronized to the clock of the particular domain.