Esd protection circuit

Abstract

A multi-fingered gate transistor formed in a substrate of one conductivity type overlying a well of a second conductivity type. Ohmic contact to the well is made by an implanted region of the second conductivity type that circumscribes the gate transistor. Ohmic contact to the substrate is made by taps located on sides of the gate structure between the gate structure and the well contact. Floating wells are located on opposite sides of the gate structure between the substrate taps and the ends of the gates to isolate these substrate taps and force current flow in the substrate under the gate transistor to be substantially perpendicular to the direction in which the gate fingers extend. This increases the potential difference between these substrate regions and source regions in the gate transistor, thereby aiding the triggering of the parasitic bipolar transistors under adjacent gate fingers into a high current state.