The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 16, 2014

Filed:

Dec. 27, 2012
Applicants:

Paul James Brown, Wakefield, CA;

Alex L. Chan, Ottawa, CA;

Inventors:

Paul James Brown, Wakefield, CA;

Alex L. Chan, Ottawa, CA;

Assignee:

Alcatel Lucent, Boulogne-Billancourt, FR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 1/03 (2006.01); H05K 1/00 (2006.01); H05K 7/20 (2006.01); H01L 21/58 (2006.01); H01L 27/04 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 27/04 (2013.01); H01L 21/58 (2013.01); H01L 2924/3511 (2013.01); H01L 23/49816 (2013.01); H01L 2924/15311 (2013.01); H01L 23/49822 (2013.01);
Abstract

An apparatus and method for temperature induced warpage compensation in an integrated circuit package is disclosed. The apparatus consists of bonded layers of material having different thermal coefficients of expansion. The bonded layers are bonded to the top of the integrated circuit package. By appropriate choice of temperature coefficients the layers of material can compensate for either convex or concave warpage. In some embodiments, the layers of material have apertures therein allowing compensation for more complex warpages. As well, in some embodiments the top layer of material does not have a planar cross-section. A method is also disclosed for manufacturing an integrated circuit package assembly. The apparatus and method provide an alternative to methods of dealing with IC package warpage known in the art.


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