The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 16, 2014

Filed:

Mar. 21, 2013
Applicant:

Kabushiki Kaisha Toshiba, Tokyo, JP;

Inventors:

Seiichi Omoto, Mie-ken, JP;

Yoshihiro Uozumi, Aichi-ken, JP;

Tadashi Iguchi, Mie-ken, JP;

Osamu Yamane, Kanagawa-ken, JP;

Kazuyuki Masukawa, Kanagawa-ken, JP;

Yoshihiro Yanai, Mie-ken, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/4763 (2006.01); H01L 27/115 (2006.01); H01L 29/792 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/788 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66666 (2013.01); H01L 27/11565 (2013.01); H01L 29/7926 (2013.01); H01L 29/66833 (2013.01); H01L 29/7827 (2013.01); H01L 29/7889 (2013.01); H01L 29/66825 (2013.01); H01L 27/11582 (2013.01); H01L 27/11575 (2013.01);
Abstract

According to one embodiment, a method for manufacturing a semiconductor device includes forming a stacked body on a substrate. The stacked body includes a plurality of first conductive layers including a metallic element as a main component and a plurality of second conductive layers including a metallic element as a main component provided respectively between the first conductive layers. The method includes making a hole to pierce the stacked body. The method includes making a slit to divide the stacked body. The method includes making a gap between the first conductive layers by removing the second conductive layers by etching via the slit or the hole. The method includes forming a memory film including a charge storage film at a side wall of the hole. The method includes forming a channel body on an inner side of the memory film inside the hole.


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