The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 16, 2014
Filed:
Sep. 20, 2011
Applicants:
Jean-luc Huguenin, Grenoble, FR;
Grégory Bidal, Grenoble, FR;
Inventors:
Jean-Luc Huguenin, Grenoble, FR;
Grégory Bidal, Grenoble, FR;
Assignee:
STMicroelectronics (Crolles 2) SAS, Crolles, FR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 29/51 (2006.01); H01L 29/49 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823462 (2013.01); H01L 29/51 (2013.01); H01L 21/82345 (2013.01); H01L 29/513 (2013.01); H01L 29/4966 (2013.01); H01L 21/28088 (2013.01);
Abstract
A method for manufacturing three types of MOS transistors in three regions of a same substrate, including the steps of: forming a first insulating layer, removing the first insulating layer from the first and second regions, forming a silicon oxide layer, depositing an insulating layer having a dielectric constant which is at least twice greater than that of silicon oxide, depositing a first conductive oxygen scavenging layer, removing the first conductive layer from the second and third regions, and annealing.