The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 16, 2014
Filed:
Jun. 25, 2013
Applicant:
SK Hynix Inc., Icheon-si Gyeonggi-do, KR;
Inventors:
Yong Seok Eun, Seongnam-si, KR;
Tae Kyun Kim, Seongnam-si, KR;
Kyong Bong Rouh, Icheon-si, KR;
Eun Shil Park, Guri-si, KR;
Assignee:
SK Hynix Inc., Gyeonggi-do, KR;
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/78 (2006.01); H01L 27/108 (2006.01); H01L 29/66 (2006.01); H01L 21/266 (2006.01); H01L 21/265 (2006.01);
U.S. Cl.
CPC ...
H01L 21/266 (2013.01); H01L 21/26586 (2013.01); H01L 29/7827 (2013.01); H01L 27/10876 (2013.01); H01L 29/66666 (2013.01); H01L 21/26513 (2013.01);
Abstract
A method for forming an impurity region of a vertical transistor includes forming an impurity ion junction region within a semiconductor substrate, and forming a trench by etching the semiconductor substrate in which the impurity ion junction region is formed. The etching process is performed to remove a portion of the impurity ion junction region, so that a remaining portion of the impurity ion junction region is exposed to a lower side wall of the trench to serve as a buried bit line junction region.