The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 09, 2014

Filed:

Nov. 20, 2009
Applicants:

Ching-chieh Wang, Yilan County, TW;

You-min Yeh, Taipei, TW;

Chin-wang Yeh, Hsinchu, TW;

Rong-liang Chiou, Hsinchu, TW;

Inventors:

Ching-Chieh Wang, Yilan County, TW;

You-Min Yeh, Taipei, TW;

Chin-Wang Yeh, Hsinchu, TW;

Rong-Liang Chiou, Hsinchu, TW;

Assignee:

Mediatek Inc., Science-Based Industrial Park, Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04N 7/16 (2011.01); H04N 21/2389 (2011.01); H04N 21/236 (2011.01); H04N 21/426 (2011.01); H04N 21/4385 (2011.01); H04N 21/2362 (2011.01); H04N 21/434 (2011.01);
U.S. Cl.
CPC ...
H04N 21/2389 (2013.01); H04N 21/23608 (2013.01); H04N 21/426 (2013.01); H04N 21/4385 (2013.01); H04N 21/2362 (2013.01); H04N 21/434 (2013.01);
Abstract

A signal processing apparatus includes a first signal processing block and a second signal processing block. The first signal processing block is utilized for processing an input signal to generate a first target processing result, including a plurality of packets initially reproduced from the input signal, to an output port of the first signal processing circuit, where each of the packets contains a corresponding packet identifier (PID). The second signal processing block has an input port coupled to the output port of the first signal processing circuit, and is utilized for processing the first target processing result according to PIDs of the packets and accordingly generating a second target processing result. There is no buffer coupled between the output port of the first signal processing circuit and the input port of the second signal processing circuit.


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