The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 09, 2014

Filed:

Dec. 06, 2012
Applicant:

Huawei Technologies Co., Ltd., Shenzhen, CN;

Inventors:

Sheng Chang, Hangzhou, CN;

Haibin Wang, Hangzhou, CN;

Jie Zhang, Shenzhen, CN;

Rongyu Yang, Hangzhou, CN;

Xinyu Hou, Hangzhou, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/20 (2006.01); G06F 11/07 (2006.01); G06F 11/14 (2006.01);
U.S. Cl.
CPC ...
G06F 11/2005 (2013.01); G06F 11/0784 (2013.01); G06F 11/1443 (2013.01); G06F 11/0724 (2013.01); G06F 11/0745 (2013.01);
Abstract

A system for implementing interconnection fault tolerance between CPUs, a first CPU and a second CPU implements interconnection through a first CPU interconnect device and a second CPU interconnect device. The system adds a data channel between a first SerDes interface of the first CPU interconnect device and a second SerDes interface of the second CPU interconnect device, and transmits link connection state information and a link control signal through the added data channel. The system monitors a link state of any one link in a CPU interconnection system, transmits the link state through the added data channel, recovers any one of the connection links when determining whether any one of the first connection link, the second connection link and the third connection link is faulty.


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