The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 09, 2014
Filed:
Jun. 10, 2010
Zhiqing Zhuang, Irvine, CA (US);
Vinay Kumar Bhasin, Irvine, CA (US);
Lawrence John Madar, Iii, San Francisco, CA (US);
Chenmin Zhang, Irvine, CA (US);
Vafa James Rakshani, Newport Coast, CA (US);
Soheyla Kamal, Newport Coast, CA (US);
Zhiqing Zhuang, Irvine, CA (US);
Jalil Fadavi-Ardekani, Newport Coast, CA (US);
Vinay Kumar Bhasin, Irvine, CA (US);
Lawrence John Madar, III, San Francisco, CA (US);
Chenmin Zhang, Irvine, CA (US);
Vafa James Rakshani, Newport Coast, CA (US);
Broadcom Corporation, Irvine, CA (US);
Abstract
A state machine and an external interface, including its associated input-outputs (IOs), are always powered on and used to manage the chip power modes and power mode transitions. The chip power modes are defined as RUN, HIBERNATE, POWERDOWN, with many more possible with this invention. For example, once the device is in HIBERNATE or POWERDOWN modes, the power supplies to the IC are either reduced, or completely disconnected except for this controller state machine. This invention's state machine and control mechanism, in response to some external 'wake up event', will bring the chip to RUN mode by managing the state of the external power supplies through its control interface. The implementation achieves small die size and extreme low power consumption.