The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 09, 2014

Filed:

Oct. 29, 2013
Applicant:

Cypress Semiconductor Corporation, San Jose, CA (US);

Inventors:

Ryan Tasuo Hirose, Colorado Springs, CO (US);

Bogdan I. Georgescu, Colorado Springs, CO (US);

Ashish Ashok Amonkar, Santa Clara, CA (US);

Vijay Raghavan, Colorado Springs, CO (US);

Cristinel Zonte, Colorado Springs, CO (US);

Sean B. Mulholland, Colorado Springs, CO (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); H01L 29/792 (2006.01); G11C 16/06 (2006.01); G11C 16/30 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G11C 16/0466 (2013.01); H01L 29/792 (2013.01); G11C 16/06 (2013.01); G11C 16/30 (2013.01); G11C 16/3418 (2013.01);
Abstract

Flash memory devices and systems are provided. One flash memory device includes an n-channel metal oxide semiconductor field-effect transistor (nMOSFET), a silicon-oxide-nitride-oxide silicon (SONOS) transistor coupled to the nMOSFET, and an isolated p-well coupled to the nMOSFET and the SONOS transistor. A flash memory system includes an array of memory devices divided into a plurality of paired sectors, a global bit line (GBL) configured to provide high voltage to each respective sector during erase and program operations coupled to each of the plurality of sectors, and a plurality of sense amplifiers coupled between a respective pair of sectors. Methods for operating a flash memory are also provided. One method includes providing high voltage, via the GBL, to the paired sectors during erase and program operations and providing low voltage, via a local bit line, to each memory device during read operations.


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