The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 09, 2014

Filed:

Dec. 21, 2011
Applicants:

Futoshi Furuta, Kokubunji, JP;

Kenichi Osada, Tokyo, JP;

Inventors:

Futoshi Furuta, Kokubunji, JP;

Kenichi Osada, Tokyo, JP;

Assignee:

Hitachi,Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); H02H 9/04 (2006.01); H01L 25/065 (2006.01); H01L 23/62 (2006.01); H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 23/62 (2013.01); H01L 23/481 (2013.01); H02H 9/046 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06565 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16225 (2013.01); H01L 2924/15311 (2013.01);
Abstract

In a stacked chip system, an IO circuit connected to a TSV pad for IO and a switch circuit constitute an IO channel in each chip, the IO channels as many as the maximum scheduled number of stacks are coupled together and connected to constitute an IO group, and the chip has one or more such IO groups. Each TSV pad for IO is connected with a through via to an IO terminal at the same position in a chip of another layer. On an interposer, if the actual number of stacks is less than the maximum scheduled number of stacks, connection pads for IO in adjacent IO groups on the interposer are connected via a conductor.


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