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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8907964 B1

PDFFull Text
Date of Patent:
Dec. 09, 2014

Filed:

Apr. 10, 2007

System and method for dynamically reconfiguring a vertex cache

Applicants:

Keith Lee, San Jose, CA (US);

Mike M. Cai, Newark, CA (US);

Inventors:

Keith Lee, San Jose, CA (US);

Mike M. Cai, Newark, CA (US);

Assignee:

Vivante Corporation, Sunnyvale, CA (US);

Attorneys:

David R. Stevens

Stevens Law Group

Primary Examiner:

Maurice L McDowell, Jr

Assistant Examiner:

Donna J Ricks

Int. Cl.
CPC ...
G09G 5/36 (2006.01); G06F 12/02 (2006.01); G06F 13/00 (2006.01); G06F 13/28 (2006.01); G06T 1/60 (2006.01); G06F 12/08 (2006.01); G06T 15/00 (2011.01); G09G 5/39 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0875 (2013.01); G06T 1/60 (2013.01); G09G 2360/128 (2013.01); G09G 5/363 (2013.01); G06F 2212/601 (2013.01); G06T 2200/28 (2013.01); G09G 5/39 (2013.01); G06T 15/005 (2013.01); G09G 2360/121 (2013.01);
Abstract

A system to process a plurality of vertices to model an object. An embodiment of the system includes a processor, a front end unit coupled to the processor, and cache configuration logic coupled to the front end unit and the processor. The processor is configured to process the plurality of vertices. The front end unit is configured to communicate vertex data to the processor. The cache configuration logic is configured to establish a cache line size of a vertex cache based on a vertex size of a drawing command.

Find Patent Forward Citations

Lee, Keith. (2014). System and method for dynamically reconfiguring a vertex cache (U.S. Patent No. 8907964). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8907964

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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