The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 09, 2014

Filed:

Feb. 05, 2009
Applicants:

Matteo Monchiero, Palo Alto, CA (US);

Jacob B. Leverich, San Mateo, CA (US);

Parthasarathy Ranganathan, Fremont, CA (US);

Norman Paul Jouppi, Palo Alto, CA (US);

Vanish Talwar, Palo Alto, CA (US);

Inventors:

Matteo Monchiero, Palo Alto, CA (US);

Jacob B. Leverich, San Mateo, CA (US);

Parthasarathy Ranganathan, Fremont, CA (US);

Norman Paul Jouppi, Palo Alto, CA (US);

Vanish Talwar, Palo Alto, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/06 (2006.01); H03K 19/00 (2006.01); H01L 25/065 (2006.01); H01L 25/18 (2006.01); H01L 23/36 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 2224/16145 (2013.01); H01L 2924/10253 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/16225 (2013.01); H01L 2225/06513 (2013.01); H03K 19/0016 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06541 (2013.01); H01L 25/18 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/13091 (2013.01); H01L 23/36 (2013.01);
Abstract

An integrated circuit package includes a digital logic die disposed on a substrate; and an interposer die stacked vertically with the digital logic die on the substrate. The interposer die includes at least one vertical transistor configured to selectively provide electrical power to a portion of the digital logic die.


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