The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 09, 2014

Filed:

Feb. 03, 2014
Applicants:

Applied Micro Circuits Corporation, San Diego, CA (US);

Volex Plc, London, GB;

Inventors:

Subhash Roy, Lexington, MA (US);

Igor Zhovnirovsky, Newton, MA (US);

Sergey Vinogradov, Moscow, RU;

Assignees:

Applied Micro Circuits Corporation, San Diego, CA (US);

Volex PLC, London, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); G01J 1/44 (2006.01); H01L 31/00 (2006.01); H01L 21/66 (2006.01); H01L 31/02 (2006.01);
U.S. Cl.
CPC ...
G01J 1/44 (2013.01); H01L 31/00 (2013.01); H01L 22/14 (2013.01); H01L 31/02019 (2013.01);
Abstract

A photodetector with a bandwidth-tuned cell structure is provided. The photodetector is fabricated from a semiconductor substrate that is heavily doped with a first dopant. A plurality of adjoining cavities is formed in the semiconductor substrate having shared cell walls. A semiconductor well is formed in each cavity, moderately doped with a second dopant opposite in polarity to the first dopant. A layer of oxide is grown overlying the semiconductor wells and an annealing process is performed. Then, metal pillars are formed that extend into each semiconductor well having a central axis aligned with an optical path. A first electrode is connected to the metal pillar of each cell, and a second electrode connected to the semiconductor substrate. The capacitance between the first and second electrodes decreases in response to forming an increased number of semiconductor wells with a reduced diameter, and forming metal pillars with a reduced diameter.


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