The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 02, 2014

Filed:

Feb. 09, 2011
Applicants:

Hidefumi Ibe, Kawasaki, JP;

Tadanobu Toba, Yokohama, JP;

Kenichi Shimbo, Yokohama, JP;

Hitoshi Taniguchi, Yokohama, JP;

Inventors:

Hidefumi Ibe, Kawasaki, JP;

Tadanobu Toba, Yokohama, JP;

Kenichi Shimbo, Yokohama, JP;

Hitoshi Taniguchi, Yokohama, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/14 (2006.01); G01R 31/00 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1405 (2013.01); G01R 31/00 (2013.01);
Abstract

A failure caused by a soft-error including MNU, of an electronic apparatus is prevented, while suppressing increase of a mounting area, power consumption, and processing time. The electronic apparatus stores data indicating the state of a flip-flop included in a sequential logic circuit within an arithmetic unit, each time when execution is performed on a check point provided for every predetermined number of instructions. When a symptom of a soft-error is detected, the apparatus sets the state of the flip-flop included in the sequential logic circuit within the arithmetic unit, based on the data stored after execution of the instruction at the immediately preceding check point, and restarts execution from the next instruction, being subsequent to the instruction associated with the immediately preceding check point.


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