The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 02, 2014

Filed:

Apr. 19, 2012
Applicants:

IN Gon Yang, Icheon-si, KR;

Duck Ju Kim, Icheon-si, KR;

Jae Won Cha, Icheon-si, KR;

Sung Hoon Ahn, Seoul, KR;

Tae Ho Jeon, Goyang-si, KR;

Inventors:

In Gon Yang, Icheon-si, KR;

Duck Ju Kim, Icheon-si, KR;

Jae Won Cha, Icheon-si, KR;

Sung Hoon Ahn, Seoul, KR;

Tae Ho Jeon, Goyang-si, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G11C 7/00 (2013.01); G11C 7/10 (2013.01);
Abstract

A semiconductor memory device includes a memory cell array configured to include memory cells, peripheral circuits configured to read out data stored in a selected memory cell in a read operation, and a controller configured to control the peripheral circuits so that the peripheral circuits sense a voltage level of the bit line when a first read voltage of the read voltages is supplied to the word line and the peripheral circuits sense voltage levels of the bit line when a second read voltage lower than the first read voltage by a specific level and a third read voltage higher than the first read voltage by the specific level are supplied to the word line in order to determine whether a threshold voltage of the selected memory cell falls within a set voltage distribution in the read operation.


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