The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 02, 2014

Filed:

Sep. 28, 2011
Applicants:

Ken Kawai, Osaka, JP;

Kazuhiko Shimakawa, Osaka, JP;

Koji Katayama, Nara, JP;

Shunsaku Muraoka, Osaka, JP;

Inventors:

Ken Kawai, Osaka, JP;

Kazuhiko Shimakawa, Osaka, JP;

Koji Katayama, Nara, JP;

Shunsaku Muraoka, Osaka, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); H01L 45/00 (2006.01); H01L 27/10 (2006.01); H01L 27/24 (2006.01); G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
H01L 27/101 (2013.01); G11C 2213/72 (2013.01); H01L 45/1233 (2013.01); G11C 2013/0073 (2013.01); G11C 2213/32 (2013.01); H01L 45/146 (2013.01); G11C 13/0064 (2013.01); G11C 2213/79 (2013.01); H01L 45/08 (2013.01); G11C 13/0007 (2013.01); G11C 2013/0083 (2013.01); G11C 13/0069 (2013.01); H01L 27/2409 (2013.01);
Abstract

In forming, an automatic forming circuit () included in a nonvolatile memory device () causes a constant current IL to flow in a selected memory cell having a considerably high initial resistance. When the forming generates a filament path in the memory cell and thereby a resistance value is decreased, a potential of a node NBL and a potential of a node Nin are also decreased. If the potentials become lower than that of a reference voltage Vref, an output NO of a difference amplifier () for detecting forming success is activated, and a forming success signal Vfp is activated after a delay time depending on the number n of flip flops FFto FFn and a clock signal CLK. Thereby, a switch transistor () is in a non-conducting state and the forming on a variable resistance element is automatically terminated.


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