The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 02, 2014
Filed:
Jul. 29, 2010
Applicants:
Michael J. Miller, Saratoga, CA (US);
Mark Baumann, Campbell, CA (US);
Richard S. Roy, Dublin, CA (US);
Inventors:
Michael J. Miller, Saratoga, CA (US);
Mark Baumann, Campbell, CA (US);
Richard S. Roy, Dublin, CA (US);
Assignee:
MoSys, Inc., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/40 (2006.01); H01L 23/50 (2006.01);
U.S. Cl.
CPC ...
H01L 23/50 (2013.01); H01L 2924/0002 (2013.01);
Abstract
A chip layout for a high speed semiconductor device is disclosed. The chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. A serial interface is centrally located to reduce latency, power and propagation delays. Stacked die that contain one or more devices with the chip layout are characterized by having improved latency, bandwidth, power consumption, and propagation delays.