The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 02, 2014
Filed:
Aug. 11, 2010
Applicants:
Klaus Goller, Regensburg, DE;
Olaf Heitzsch, Coswig, DE;
Marion Nichterwitz, Dresden, DE;
Inventors:
Assignee:
Infineon Technologies AG, Neubiberg, DE;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); G03F 9/00 (2006.01); G03F 7/20 (2006.01); H01L 23/544 (2006.01);
U.S. Cl.
CPC ...
G03F 9/7084 (2013.01); G03F 9/7076 (2013.01); H01L 2223/54453 (2013.01); G03F 7/70633 (2013.01); H01L 23/544 (2013.01); G03F 9/708 (2013.01);
Abstract
An integrated circuit arrangement is disclosed having a wiring indentation and an auxiliary indentation in a dielectric layer. The wiring indentation contains a metal through which current flows during operation of the circuit arrangement. The auxiliary indentation contains a metal through which an electric current does not flow during operation of the circuit arrangement. The auxiliary indentation serves as an alignment mark during the production of the integrated circuit arrangement.