The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 02, 2014
Filed:
Feb. 10, 2011
Oliver Hilt, Schöneiche, DE;
Hans-joachim Wuerfl, Zeuthen, DE;
Oliver Hilt, Schöneiche, DE;
Hans-Joachim Wuerfl, Zeuthen, DE;
Forschungsverbund Berlin E.V., Berlin, DE;
Abstract
The invention relates to semiconductor components, in particular to a scalable construction for lateral semiconductor components having high current-carrying capacity. A transistor cell according to the invention comprises a control electrode (), a plurality of source fields () and a plurality of drain fields (). The control electrode completely encloses at least one of the source fields or drain fields. A transistor according to the invention comprises a plurality of transistor cells on a substrate, each of which comprises a source contact field () and/or a drain contact field (). The source contact fields are conductively connected to each other on the other side of the substrate and the drain contact fields are likewise conductively connected to each other on the other side of the substrate. The method according to the invention for producing a transistor comprises the following steps: providing a substrate; forming a plurality of transistor cells on the substrate, each of which comprises a control electrode, a plurality of source fields and a plurality of drain fields; conductively connecting the control electrodes to each other; forming a source contact field and/or a drain contact field in each transistor cell; conductively connecting the source contact fields of each transistor cell to a source contact field; conductively connecting the drain fields of each transistor cell to a drain contact field; forming at least one bump () on each of the source contact fields and on each of the drain contact fields; providing a circuit board; conductively connecting the bumps of the source contact fields to each other by means of conductive tracks on the circuit board; and conductively connecting the bumps of the drain contact fields to each other by means of conductive tracks on the circuit board. The arrangement of the bumps and the conductive tracks on the circuit board makes a low semiconductor surface assignment by wiring possible. The arrangement according to the invention of the source fields, drain fields and control electrodes relative to the bumps makes a low heat resistance possible between the active transistor regions and the bumps.