The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 02, 2014

Filed:

Jan. 18, 2012
Applicants:

Fuad E. Doany, Katonah, NY (US);

Benjamin G. Lee, New York, NY (US);

Alexander V. Rylyakov, Mount Kisco, NY (US);

Clint L. Schow, Ossining, NY (US);

Marc A. Taubenblatt, Pleasantville, NY (US);

Inventors:

Fuad E. Doany, Katonah, NY (US);

Benjamin G. Lee, New York, NY (US);

Alexander V. Rylyakov, Mount Kisco, NY (US);

Clint L. Schow, Ossining, NY (US);

Marc A. Taubenblatt, Pleasantville, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 33/00 (2010.01); H01L 29/18 (2006.01); H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Processing for a silicon photonics wafer is provided. A silicon photonics wafer that includes an active silicon photonics layer, a thin buried oxide layer, and a silicon substrate is received. The thin buried oxide layer is located between the active silicon photonics layer and the silicon substrate. An electrical CMOS wafer that includes an active electrical layer is also received. The active silicon photonics layer of the silicon photonics wafer is flip chip bonded to the active electrical layer of the electrical CMOS wafer. The silicon substrate is removed exposing a backside surface of the thin buried oxide layer. A low-optical refractive index backing wafer is added to the exposed backside surface of the thin buried oxide layer. The low-optical refractive index backing wafer is a glass substrate or silicon substrate wafer. The silicon substrate wafer includes a thick oxide layer that is attached to the thin buried oxide layer.


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