The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 02, 2014

Filed:

Dec. 26, 2007
Applicant:

Steve Xin Liang, San Diego, CA (US);

Inventor:

Steve Xin Liang, San Diego, CA (US);

Assignee:

Skyworks Solutions, Inc., Woburn, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/72 (2006.01); B81B 7/00 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01); H03H 9/05 (2006.01);
U.S. Cl.
CPC ...
B81B 7/0077 (2013.01); H01L 23/315 (2013.01); H01L 24/81 (2013.01); H03H 9/0523 (2013.01); H03H 9/059 (2013.01); B81C 2203/0109 (2013.01); B81C 2203/019 (2013.01); H01L 2924/01046 (2013.01); H01L 2924/01078 (2013.01); H01L 2924/01079 (2013.01); H01L 2924/14 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19042 (2013.01); H01L 2924/19043 (2013.01); H01L 23/3121 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 2224/1134 (2013.01); H01L 2224/11462 (2013.01); H01L 2224/13082 (2013.01); H01L 2224/131 (2013.01); H01L 2224/13144 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/81139 (2013.01); H01L 2224/8114 (2013.01); H01L 2224/81191 (2013.01); H01L 2224/81207 (2013.01); H01L 2224/814 (2013.01); H01L 2224/81439 (2013.01); H01L 2224/81444 (2013.01); H01L 2224/81447 (2013.01); H01L 2224/81464 (2013.01); H01L 2224/8183 (2013.01); H01L 2924/00013 (2013.01); H01L 2924/014 (2013.01); B81C 2203/0118 (2013.01); H01L 2224/16227 (2013.01); H01L 2924/01029 (2013.01); H01L 2224/10135 (2013.01); H01L 2224/16225 (2013.01);
Abstract

A flip chip semiconductor packaging device and method that incorporates in situ formation of cavities underneath selected portions of a die during a flip chip die bonding process. A method of flip chip semiconductor component packaging includes providing a die having a first surface, forming a barrier on first surface of the die, the barrier at least partially surrounding a designated location on the first surface of the die, bonding the die to a substrate in a flip chip configuration, and flowing molding compound over the die and over at least a portion of the substrate. Bonding the die to the substrate includes causing contact between the barrier and the substrate such that flow of the molding compound is blocked by the barrier to provide a cavity between the die and the substrate, the cavity being proximate the designated location on the first surface of the die.


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