The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2014

Filed:

Dec. 06, 2011
Applicants:

Shuhei Matsumoto, Yokohama, JP;

Hironori Inoue, Ebina, JP;

Shintaro Wada, Sakura, JP;

Inventors:

Shuhei Matsumoto, Yokohama, JP;

Hironori Inoue, Ebina, JP;

Shintaro Wada, Sakura, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/46 (2006.01); G06F 11/34 (2006.01);
U.S. Cl.
CPC ...
G06F 11/3423 (2013.01); G06F 11/3433 (2013.01); G06F 2201/88 (2013.01);
Abstract

The method of calculating the processor utilization for each of logical processors in a computer, including the steps of: dividing the computation interval in which the processor utilization by each logical processor is to be calculated into a single task mode (ST) execution interval and a multitask mode (MT) execution interval, appropriately calculating them based on the before-and-after relation between two times; and adding the MT execution interval multiplied by a predetermined MT mode processor resource assignment ratio to the ST mode execution interval to obtain the processor utilization for the calculation-targeted logical processor in the computation interval.


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