The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2014

Filed:

Dec. 23, 2009
Applicants:

Donald R. Desota, Liberty Hill, TX (US);

Rajendra D. Panda, Austin, TX (US);

Venkat R. Indukuru, Austin, TX (US);

Joseph H. Robichaux, Round Rock, TX (US);

Robert H. Bell, Jr., Austin, TX (US);

Steven P. Hartman, Round Rock, TX (US);

Inventors:

Donald R. Desota, Liberty Hill, TX (US);

Rajendra D. Panda, Austin, TX (US);

Venkat R. Indukuru, Austin, TX (US);

Joseph H. Robichaux, Round Rock, TX (US);

Robert H. Bell, Jr., Austin, TX (US);

Steven P. Hartman, Round Rock, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/46 (2006.01); G06F 13/16 (2006.01); G06F 9/50 (2006.01);
U.S. Cl.
CPC ...
G06F 9/5011 (2013.01); G06F 13/16 (2013.01); G06F 9/5083 (2013.01);
Abstract

According to one aspect of the present disclosure a system and computer program product for managing memory access is disclosed. The system includes a plurality of memory controllers each configured to maintain memory databus utilization by a corresponding processor at or below a threshold to maintain memory databus utilization of the system at or below a system threshold. The system also includes a service processor configured to receive memory databus utilization data from the memory controllers and programmed to, in response to determining that memory databus utilization for at least one of the processors is below its threshold, reallocate at least a portion of unused databus utilization from the at least one processor to at least one of the other processors.


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