The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2014

Filed:

Jul. 06, 2011
Applicant:

Hiroyuki Morishita, Osaka, JP;

Inventor:

Hiroyuki Morishita, Osaka, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/46 (2006.01); G06F 9/26 (2006.01); G06F 13/00 (2006.01); G06F 12/00 (2006.01); G06F 7/00 (2006.01); G06F 9/48 (2006.01); G06F 9/38 (2006.01); G06F 9/30 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3009 (2013.01); G06F 9/4812 (2013.01); G06F 9/3851 (2013.01); G06F 9/4843 (2013.01);
Abstract

Provide is a processor that can maintain a dependency relationship between a plurality of instructions and one read instruction. The processor comprises: a setting unit configured to set, when an instruction that exists at a location ensuring that writing into a memory area has been completed is executed, usage information indicating whether writing into the memory area has been completed such that the usage information indicates that writing into a memory area during execution of one thread has been completed; and a control unit configured to (i) perform execution of a read instruction to read data stored in the memory area when the usage information indicates that writing into the memory area during execution of the one thread has been completed, and (ii) suppress execution of the read instruction when the usage information indicates that writing into the memory area during execution of the one thread has not been completed.


Find Patent Forward Citations

Morishita, Hiroyuki. (2014). Processor that executes a plurality of threads by promoting efficiency of transfer of data that is shared with the plurality of threads (U.S. Patent No. 8898671). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8898671

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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