The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2014

Filed:

Nov. 15, 2013
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Rani Abou Ghaida, San Jose, CA (US);

Ahmed Mohyeldin, San Jose, CA (US);

Piyush Pathak, Fremont, CA (US);

Swamy Muddu, Milapitas, CA (US);

Vito Dai, Santa Clara, CA (US);

Luigi Capodieci, Santa Cruz, CA (US);

Assignee:

GlobalFoundries Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5081 (2013.01); G06F 17/5077 (2013.01);
Abstract

A process and apparatus are provided for automated pattern-based semiconductor design layout correction. Embodiments include: determining a portion of a layout of an IC design, the portion comprising a first pattern of a plurality of routes connecting a plurality of design connections; determining one or more sets of the plurality of design connections based on the plurality of routes; and determining, by a processor, a second pattern of a plurality of routes connecting the plurality of design connections within the portion based on the one or more sets.


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