The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2014

Filed:

Nov. 07, 2008
Applicants:

Chaiyasit Manovit, Mountain View, CA (US);

Paul Nicholas Loewenstein, Palo Alto, CA (US);

Inventors:

Chaiyasit Manovit, Mountain View, CA (US);

Paul Nicholas Loewenstein, Palo Alto, CA (US);

Assignee:

Oracle America, Inc., Redwood City, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 9/46 (2006.01); G06F 9/52 (2006.01); G06F 12/12 (2006.01); G06F 12/08 (2006.01);
U.S. Cl.
CPC ...
G06F 12/127 (2013.01); G06F 9/528 (2013.01); G06F 12/0842 (2013.01);
Abstract

Methods and apparatuses are disclosed that allow for improved speculation success in execute ahead microprocessors. In some embodiments, the method may include speculatively executing a first thread of a program code while a second thread of the program code is executing, determining if a load request is serviceable from a cache line within a cache, and in the event that the load request is serviceable from the cache line, associating a first indicator bit with the cache line. The method also may include determining whether the cache line associated with the first indicator bit has been evicted, and in the event that the cache line is evicted, allowing speculative execution of the first thread to continue.


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