The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 25, 2014
Filed:
Jul. 29, 2004
Gary Belgrave Gostin, Plano, TX (US);
Larry N. Mcmahan, Fremont, CA (US);
Michael A. Schroeder, Dallas, TX (US);
Craig W. Warner, Addison, TX (US);
Richard W. Adkisson, Dallas, TX (US);
Huai-ter Victor Chong, Plano, TX (US);
David M. Binford, Allen, TX (US);
Mark Edward Shaw, Garland, TX (US);
Joe P. Cowan, Collins, CO (US);
Thierry Fevrier, Gold River, CA (US);
Arad Rostampour, Collins, CO (US);
Gary Belgrave Gostin, Plano, TX (US);
Larry N. McMahan, Fremont, CA (US);
Michael A. Schroeder, Dallas, TX (US);
Craig W. Warner, Addison, TX (US);
Richard W. Adkisson, Dallas, TX (US);
Huai-Ter Victor Chong, Plano, TX (US);
David M. Binford, Allen, TX (US);
Mark Edward Shaw, Garland, TX (US);
Joe P. Cowan, Collins, CO (US);
Thierry Fevrier, Gold River, CA (US);
Arad Rostampour, Collins, CO (US);
Hewlett-Packard Development Company, L.P., Houston, TX (US);
Abstract
A computing device having partitions, and a method of communicating between partitions, are disclosed wherein at least one partition comprises: at least one register substantially always accessible to other partitions and capable of defining an address area; at least one address area that may be accessible to other partitions and is capable of being defined by the at least one register; and address areas other than the at least one accessible address area that are not accessible to other partitions. A method of processing interrupts comprising receiving an interrupt, assessing the origin of the interrupt, accepting, rejecting, or further assessing the interrupt, depending on its origin, when further assessing the interrupt, accepting or rejecting the interrupt depending on its contents, and forwarding accepted interrupts but not rejected interrupts to a target processor, and a device carrying out that method are also disclosed.