The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2014

Filed:

Mar. 14, 2013
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Xinwei Wang, Dunstable, MA (US);

Yongrong Zuo, Chelmsford, MA (US);

Xiangdong Zhang, Westford, MA (US);

Marc Gerald DiCicco, Dunstable, MA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 17/00 (2006.01); H03F 3/45 (2006.01); G01R 21/14 (2006.01); H03F 3/24 (2006.01); H03G 1/04 (2006.01); H03G 3/30 (2006.01);
U.S. Cl.
CPC ...
H04B 17/0062 (2013.01); H03F 2203/45292 (2013.01); H03F 3/45183 (2013.01); H03F 2200/456 (2013.01); H03F 2203/45302 (2013.01); H03F 2200/447 (2013.01); H03G 1/04 (2013.01); H03F 2200/453 (2013.01); H03F 2200/465 (2013.01); H03F 3/45188 (2013.01); H03F 2203/45481 (2013.01); G01R 21/14 (2013.01); H03F 2203/45156 (2013.01); H03F 3/245 (2013.01); H03F 2203/45112 (2013.01); H03G 3/3036 (2013.01);
Abstract

Power detectors with temperature compensation and having improved accuracy over temperature are disclosed. In an aspect of the disclosure, variations of a power detector gain over temperature is reduced by varying both the gate and drain voltages of MOS transistors within a power detector. In an exemplary design, an apparatus includes at least one MOS transistor, which receives an input signal, detects the power of the input signal based on a power detection gain, and provides an output signal indicative of the power of the input signal. The at least one MOS transistor is applied a variable gate bias voltage and a variable drain bias voltage in order to reduce variations of the power detection gain over temperature. At least one additional MOS transistor may receive a second variable gate bias voltage and provide the variable drain bias voltage for the at least one MOS transistor.


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