The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2014

Filed:

Dec. 31, 2010
Applicants:

Edmund Chen, Sunnyvale, CA (US);

Ramanathan Lakshmikanthan, Santa Clara, CA (US);

Ranjit Rozario, San Jose, CA (US);

Brian Alleyne, Los Gatos, CA (US);

Stephen Chow, Monte Sereno, CA (US);

Patrick Wang, Palo Alto, CA (US);

Edward Ho, Fremont, CA (US);

Thomas Yip, Los Gatos, CA (US);

Sun Den Chen, San Jose, CA (US);

Michael Feng, Sunnyvale, CA (US);

Inventors:

Edmund Chen, Sunnyvale, CA (US);

Ramanathan Lakshmikanthan, Santa Clara, CA (US);

Ranjit Rozario, San Jose, CA (US);

Brian Alleyne, Los Gatos, CA (US);

Stephen Chow, Monte Sereno, CA (US);

Patrick Wang, Palo Alto, CA (US);

Edward Ho, Fremont, CA (US);

Thomas Yip, Los Gatos, CA (US);

Sun Den Chen, San Jose, CA (US);

Michael Feng, Sunnyvale, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 12/54 (2006.01); H04L 12/861 (2013.01); H04L 12/801 (2013.01); H04L 12/851 (2013.01); H04L 12/823 (2013.01);
U.S. Cl.
CPC ...
H04L 49/9073 (2013.01); H04L 47/12 (2013.01); H04L 47/2441 (2013.01); H04L 47/32 (2013.01); H04L 49/9036 (2013.01); H04L 49/9063 (2013.01); H04L 49/9078 (2013.01);
Abstract

Embodiments of the invention include a method for avoiding memory bandwidth utilization during packet processing. The packet processing core receives a plurality of packets. The packet processing core identifies the packet's quality of service (QoS) descriptor. The packet processing core determines that at least one packet should be moved to an off-chip packet stored prior to the packet being transmitted to the egress port. The packet processing core bases that determination, at least in part, on the packet's QoS descriptor. The packet processing core moves the determined packets to the off-chip packet store. The packet processing core determines that at least one packet should not be moved to the off-chip packet store prior to the packet being transmitted to the egress port. This determination is also made, at least in part, based on the packet's QoS descriptor.


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