The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2014

Filed:

Dec. 14, 2012
Applicant:

Genusion, Inc., Amagasaki, JP;

Inventors:

Natsuo Ajika, Hyogo, JP;

Shoji Shukuri, Hyogo, JP;

Satoshi Shimizu, Hyogo, JP;

Taku Ogura, Hyogo, JP;

Assignee:

Genusion, Inc., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/10 (2006.01); H01L 27/115 (2006.01); G11C 16/12 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G11C 16/10 (2013.01); H01L 27/115 (2013.01); G11C 16/12 (2013.01); G11C 16/0483 (2013.01); H01L 27/11524 (2013.01);
Abstract

According to an aspect of the present invention, it is provided: a nonvolatile semiconductor memory device comprising: a plurality of bit lines arranged in a first direction; a plurality of source lines arranged in the first direction, the plurality of source lines being parallel to the plurality of bit lines, the plurality of source lines being distinct from the plurality of bit lines; a plurality of memory gate lines arranged in a second direction perpendicular to the first direction; a plurality of memory cells arranged in a matrix, each of the plurality of memory cells including a p type MIS nonvolatile transistor having a first terminal, a second terminal, a channel between the first terminal and the second terminal, a gate insulation film formed on the channel, a gate electrode connected to one corresponding memory gate line of the plurality of memory gate lines, and a carrier storage layer formed between the gate insulation film and the gate electrode, the first terminal being connected to one corresponding bit line of the plurality of bit lines and the second terminal being connected to one corresponding source line of the plurality of source lines.


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