The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2014

Filed:

May. 12, 2008
Applicants:

Timothy Von Werne, London, GB;

Catherine Mary Ramsdale, Cambridgeshire, GB;

Henning Sirringhaus, Cambridgeshire, GB;

Inventors:

Timothy Von Werne, London, GB;

Catherine Mary Ramsdale, Cambridgeshire, GB;

Henning Sirringhaus, Cambridgeshire, GB;

Assignee:

Plastic Logic Limited, Cambridge, Cambridgeshire, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 51/05 (2006.01); H01L 21/312 (2006.01); H01L 51/00 (2006.01);
U.S. Cl.
CPC ...
H01L 51/0541 (2013.01); H01L 51/052 (2013.01); H01L 51/0529 (2013.01); H01L 51/0035 (2013.01); H01L 21/312 (2013.01);
Abstract

A technique for isolating electrodes on different layers of a multilayer electronic device across an array containing more than 100000 devices on a plastic substrate. The technique comprises depositing a bilayer of a first dielectric layer () of a solution-processible polymer dielectric and a layer of parylene () to isolate layers of conductor or semiconductor on different levels of the device. The density of defects located in the active area of one of the multilayer electronic devices is typically more than 1 in 100000.


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