The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 25, 2014
Filed:
Apr. 13, 2012
Hyung-kyu Lee, Edina, MN (US);
Youngpil Kim, Eden Prairie, MN (US);
Peter Nicholas Manos, Eden Prairie, MN (US);
Maroun Khoury, Burnsville, MN (US);
Dadi Setiadi, Edina, MN (US);
Chulmin Jung, Edina, MN (US);
Hsing-kuen Liou, Plymouth, MN (US);
Paramasiyan Kamatchi Subramanian, Edina, MN (US);
Yongchul Ahn, Eagan, MN (US);
Jinyoung Kim, Edina, MN (US);
Antoine Khoueir, Apple Valley, MN (US);
Hyung-Kyu Lee, Edina, MN (US);
YoungPil Kim, Eden Prairie, MN (US);
Peter Nicholas Manos, Eden Prairie, MN (US);
Maroun Khoury, Burnsville, MN (US);
Dadi Setiadi, Edina, MN (US);
Chulmin Jung, Edina, MN (US);
Hsing-Kuen Liou, Plymouth, MN (US);
Paramasiyan Kamatchi Subramanian, Edina, MN (US);
Yongchul Ahn, Eagan, MN (US);
Jinyoung Kim, Edina, MN (US);
Antoine Khoueir, Apple Valley, MN (US);
Seagate Technology LLC, Cupertino, CA (US);
Abstract
The present invention is generally directed to an apparatus with embedded (bottom side) control lines for vertically stacked semiconductor elements. In accordance with various embodiments, a first semiconductor wafer is provided with a first facing surface on which a first conductive layer is formed. The first semiconductor wafer is attached to a second semiconductor wafer to form a multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive wafer is formed. The first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure. Portions of the combined conductive layer are removed to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure.