The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 25, 2014
Filed:
Feb. 02, 2012
Thierry Pinguet, Cardiff-by-the-Sea, CA (US);
Steffen Gloeckner, San Diego, CA (US);
Peter DE Dobbelaere, San Diego, CA (US);
Sherif Abdalla, Carlsbad, CA (US);
Daniel Kucharski, Carlsbad, CA (US);
Gianlorenzo Masini, Carlsbad, CA (US);
Kosei Yokoyama, San Diego, CA (US);
John Guckenberger, San Diego, CA (US);
Attila Mekis, Carlsbad, CA (US);
Thierry Pinguet, Cardiff-by-the-Sea, CA (US);
Steffen Gloeckner, San Diego, CA (US);
Peter De Dobbelaere, San Diego, CA (US);
Sherif Abdalla, Carlsbad, CA (US);
Daniel Kucharski, Carlsbad, CA (US);
Gianlorenzo Masini, Carlsbad, CA (US);
Kosei Yokoyama, San Diego, CA (US);
John Guckenberger, San Diego, CA (US);
Attila Mekis, Carlsbad, CA (US);
Luxtera, Inc., Carlsbad, CA (US);
Abstract
Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on two CMOS wafers with different silicon layer thicknesses for the photonic and electronic devices bonded to at least a portion of each of the wafers together, where a first of the CMOS wafers includes the photonic devices and a second of the CMOS wafers includes the electronic devices. The electrical devices may be coupled to optical devices utilizing through-silicon vias. The different thicknesses may be fabricated utilizing a selective area growth process. Cladding layers may be fabricated utilizing oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafers. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions.